1. Field of the Invention
The present invention relates to an imaging apparatus.
Priority is claimed on Japanese Patent Application No. 2011-286027, filed Dec. 27, 2011, the content of which is incorporated herein by references.
2. Description of Related Art
Recently, imaging devices such as a digital camera, include auto focus (AF) functionality. As a method of realizing the AF function in a conventional imaging apparatus, the position of a focus lens is sequentially moved in a certain direction based on a pixel signal output from a solid-state imaging device (hereinafter referred to as an “image sensor”). Thus, a so-called imager AF using hill-climbing control to detect a focusing position on a subject is known. In the imager AF, an AF evaluation value for control of AF is generated based on a pixel signal output from the image sensor in real time, and the position of the focus lens is controlled based on the generated AF evaluation value (see Japanese Unexamined Patent Application, First Publication No. 2005-252484).
FIG. 10 is a block diagram illustrating a schematic configuration of a conventional imaging apparatus. In FIG. 10, the imaging apparatus includes an image sensor, an imaging processing unit, an image processing unit, a DRAM (Dynamic Random Access Memory) controller, a DRAM, a display processing unit, a display device, and a CPU. Also, the imaging processing unit, the image processing unit, the display processing unit, the CPU, and the DRAM controller included in the imaging apparatus are connected to a common data bus, and the respective components perform, via the data bus, data delivery when performing a process. Further, in FIG. 10, a schematic internal configuration of the imaging processing unit is also shown. In FIG. 10, the imaging processing unit includes an imaging IF (interface) unit, a preprocessing unit, an AE evaluation value generation unit, an AWB evaluation value generation unit, an AF evaluation value generation unit, and an output DMA (Direct Memory Access) unit.
In the conventional imaging apparatus illustrated in FIG. 10, the imaging IF unit acquires a pixel signal from the image sensor, and outputs the acquired pixel signal as image data to the preprocessing unit. The preprocessing unit performs various processes on the image data input from the imaging IF unit. In FIG. 10, an example of the preprocessing unit including three processing units that perform the respective processes is illustrated. The preprocessing unit outputs final image data obtained by the respective processing units sequentially performing the processes to the AE evaluation value generation unit, the AWB evaluation value generation unit, the AF evaluation value generation unit, and the output DMA unit.
The output DMA unit stores the image data input from the preprocessing unit in the DRAM via the DRAM controller. Here, the image data stored in the DRAM becomes original image data that is image-processed by the image processing unit later.
Further, the AF evaluation value generation unit generates an AF evaluation value based on the image data input from the preprocessing unit. The AF evaluation value generation unit stores the generated AF evaluation value in the DRAM via the DRAM controller. The CPU performs control of AF in the conventional imaging apparatus, that is, control of a position of a focus lens using the AF evaluation value stored in the DRAM.
Further, the AE evaluation value generation unit and the AWB evaluation value generation unit are evaluation value generation units that generate evaluation values for control of auto exposure (AE), auto white balance (AWB) and the like as photography control other than the AF in the conventional imaging apparatus. The AE evaluation value generation unit and the AWB evaluation value generation unit generate an AE evaluation value and an AWB evaluation value, respectively, based on the image data input from the preprocessing unit, similar to the AF evaluation value generation unit. The AE evaluation value generation unit and the AWB evaluation value generation unit store the generated AE and AWB evaluation values in the DRAM via the DRAM controller. The CPU performs control of AE and AWB in the conventional imaging apparatus using the AE evaluation value and the AWB evaluation value stored in the DRAM.
The AF evaluation value generation unit, the AE evaluation value generation unit, and the AWB evaluation value generation unit may be configured to hold the generated AF, AE, and AWB evaluation values in registers of the respective evaluation values generation units instead of storing the generated AF, AE, and AWB evaluation values in the DRAM, respectively. In the case of such a configuration, after receiving a notification indicating that the generation of the evaluation values is completed from the respective evaluation values generation units, the CPU reads the respective evaluation values held in the registers in the respective evaluation value generation units, and performs control of AF, AE, and AWB in the imaging apparatus using the respective read evaluation values.
With such a configuration, each time the pixel signal is acquired from the image sensor, the conventional imaging apparatus generates the AF evaluation value, the AE evaluation value, and the AWB evaluation value and performs control of photography in the imaging apparatus.
Further, in the conventional imaging apparatus, there is a need for a high-speed AF function, that is, a high focusing speed. Accordingly, in a conventional imaging apparatus with an imager AF, a method of increasing a speed at which a pixel signal is read from the image sensor, that is, increasing a frame rate, is adopted as a method for realizing a high focusing speed. More AF evaluation values, one being obtained each time the pixel signal is acquired from the image sensor, that is, for each captured frame, can be obtained by increasing the frame rate.
However, the pixel signal of each frame acquired from the image sensor is used for cases other than control for photography in the imaging apparatus, of the AF evaluation value or the like. For example, a so-called live view function of displaying a video for confirmation of a subject to be photographed on a display device such as a TFT (thin film transistor) liquid crystal display or an EVF (electronic view finder) mounted on the imaging apparatus is mounted in the conventional imaging apparatus. In this live view function, image data of each frame for display on the display device is generated from the pixel signal of each frame acquired from the image sensor, and the image data of respective frames is sequentially displayed on the display device for each frame.
FIG. 11 is a timing chart illustrating an example of a schematic timing of the image sensor and the display device included in the conventional imaging apparatus. In the following description, in order to discriminate a frame rate of the image sensor from a frame rate of the display device, a frame rate at which a pixel signal is acquired from the image sensor is referred to as an “imaging frame rate,” and a frame rate at which the display device displays an image is referred to as a “display frame rate.” In FIG. 11, there is a case in which the imaging frame rate of the image sensor is 120 fps (frame/sec), and the display frame rate of the display device is 60 fps. In this case, a timing relationship between a captured image that is image data according to the pixel signal acquired from the image sensor and a display image that is the image data displayed on the display device is illustrated.
In FIG. 11, “vertical synchronization signal of image sensor” is a signal indicating a timing at which acquisition of a pixel signal of each frame from the image sensor starts. “Vertical synchronization signal of display device” is a signal indicating a timing at which the display device starts display of the image of each frame. Further, in FIG. 11, a period of “AF process” is a period in which an AF evaluation value generation unit included in the imaging apparatus generates an AF evaluation value based on a captured image. In FIG. 11, a case in which a timing of “vertical synchronization signal of image sensor” and a timing of “vertical synchronization signal of display device” are synchronized to facilitate a comparison of timing relationships between the captured image and the display image is illustrated.
When the imaging frame rate of the image sensor and the display frame rate of the display device in the conventional imaging apparatus differ from each other, a method of decimating a captured image and displaying a resultant image on the display device is adopted as illustrated in FIG. 11. In FIG. 11, since the display frame rate is half of the imaging frame rate, a captured image decimated in half in units of frames becomes a display image.
Further, for example, technologies such as technologies in Japanese Unexamined Patent Application, First Publication Nos. 2005-39710 and 2007-336599 are disclosed as technologies for displaying a synthesized image. In the technologies disclosed in Japanese Unexamined Patent Application, First Publication Nos. 2005-39710 and 2007-336599, the number of frames of a captured image to be synthesized is changed according to a display frame rate for display on a display device.